- Develop FPGA requirements based on flowed down requirements and expand these requirements to include derived requirements
- Develop FPGA architecture supporting flowed down and derived requirements.
- Develop FPGAs code meeting requirements.
- Verify FPGA timing margins and perform full simulations using ModelSim or other equivalent design tools.
- Perform analysis to show design meets throughput and timing meeting requirements.
- Verify design using simulation or in a lab environment working closely with support personnel during the design and verification process.
- Develop material for and participated in FPGA Design reviews.
- Strong VHDL skills - Verilog and system Verilog is helpful.
- Current TS/SCI Clearance
- Familiarity with SynplifyPRO, Libero SoC, LiberoIDE, Designer, Aldec Riviera PRO.
- Experience with multiple clock domains.
- Experience partitioning designs.
- Strong verbal and written communications skills
- Strong interpersonal skills
- A Bachelor’s Degree (BS) in Electrical Engineering or related field or equivalent experience is required. BS degree and 8 or more years of related experience is required.